1. Field of the Invention
This invention relates to a display apparatus in which a large number of display elements such as luminescent cells or cells for controlling light intensity are arranged in a matrix form, and which displays images, characters, graphics or the like.
2. Description of Related Art
FIG. 1 is a block diagram illustrating the configuration of a typical example of such a display apparatus which is disclosed in U.S. Pat. No. 4,498,081.
The display apparatus of FIG. 1 will be described. At first, an analog composite video signal 1 is inputted to a synchronizing separator circuit 2A. This synchronizing separator circuit 2A separates from the composite video signal 1 a horizontal synchronizing signal and a vertical synchronizing signal which are in turn supplied to a write control circuit 4. A chrominance demodulator circuit 2B independently separates luminance signals for red, green and blue from a separated video signal and outputs them in the form of analog signals to an A/D (analog to digital) converter 3. The A/D converter 3 generates a digital signal for each color in accordance with the corresponding luminance signal. A data multiplexer 5 which receives these digital signals selects one of them successively according to the color arrangement of cathode ray tubes 21 on a display board. The selected digital signals are transferred as the write data to a data latch circuit 6 as they are, and temporarily latched therein until the timing of writing data into a video data memory 8 occurs.
In accordance with the input synchronizing signal, the write control circuit 4 generates a signal for specifying an address in the video data memory 8, i.e., a memory write address signal, and sends it to an address multiplexer 7. The address multiplexer 7 receives a signal from a memory read and write controller 14 which is adapted to set the time sharing of the write period and the read period of each of the video data memory 8, a graphic data memory 9 and a blanking data memory 10, and in response to this signal sends the memory write address signal to the video data memory 8 only during the write period, thereby storing the latched write data into a desired address.
The video data memory 8 comprises a RAM (random access memory) having memory elements the number of which corresponds to the number of ray tubes 21 arranged in a matrix form on the display board. In the video data memory 8, the data are written in positions corresponding to the respective memory write address signals. Similarly, characters and graphics are displayed by using the graphic data memory 9 corresponding to the video data memory 8, and characters or the like are displayed by blanking video signals from the video data memory 8 with data from the blanking data memory 10.
On the other hand, only a particular region of the display board is controlled by using a video mode memory 11, a graphic mode memory 12 and a blanking mode memory 13, so that, in one or more specified areas of the particular region, data from the video data memory 8, the graphic data memory 9 or the blanking data memory 10 are locked. Data from the video mode memory 11 are supplied through an OR circuit 31 to an inhibit terminal of an AND circuit 32, so that data from the video data memory 8 which correspond to an area set by a data processor 16 are locked to the video mode memory 11. Data from the graphic mode memory 12 are supplied to an inhibit terminal of an AND circuit 30, so that data from the graphic data memory 9 which correspond to an area set by the graphic mode memory 12 are locked. Data from the blanking mode memory 13 are supplied to an inhibit terminal of an AND circuit 29, so that data from the blanking data memory 10 which correspond to an area set by the blanking mode memory 13 are locked.
These locking operations can be carried out individually or together depending upon the mode of an automatic-manual switching circuit 17 which is set to the manual mode or the automatic mode. In all the memories 9, 10, 11, 12 and 13 other than the video data memory 8, addresses are specified externally as desired by the data processor 16 and data are written therein with the same timing as that employed for the video data memory 8.
Data read out from the video data memory 8, graphic data memory 9 and blanking data memory 10 are supplied through an OR circuit 33 to a data comparator 18.
A display set and reset address generating circuit 15 receives a timing signal from the memory read and write controller 14, and generates an address signal for reading data from a memory which is in turn supplied to the address multiplexer 7. Upon receiving the timing signal from the memory read and write controller 14, the address multiplexer 7 opens its gate for a predetermined read period. In this operation, reading address signals are supplied to the video data memory 8, and the reading operation is carried out.
Using these reading address signals, all the memory elements of the video data memory 8 are sequentially addressed so that all stored data are read out. When signals are to be read out from the graphic data memory 9 and blanking data memory 10, reading address signals for each of the memories 9 and 10 are supplied in the same manner as the above at every predetermined read period to the address multiplexer 7.
In synchrony with the timing signal from the memory read and write controller 14, the display set and reset address generating circuit 15 supplies "on" discriminating comparison data for the cathode ray tube 21 to the data comparator 18. The data comparator 18 sequentially compares read-out data with the comparison data of each step, and outputs "on" and "off" signals to a data latch circuit 19 according to the levels of the read-out signals.
In response to these signals, column drive circuits 23 are driven to control the brightness of the cathode ray tubes 21. More specifically, a D-type flip-flop 20 is coupled to the cathode of each of the cathode ray tubes 21 through a transistor 22, and the output of the respective column drive circuit 23 is inputted to the data input terminals D of the flip-flops 20. The display set and reset address generating circuit 15 generates an address signal and a set signal, and the set signal is received by a set address discriminating circuit 24 corresponding to the address. The set signal is outputted from a line drive circuit 25 of the corresponding line to the terminals T of the flip-flops 20 which are coupled to the cathode ray tubes 21 in the corresponding line. According to the set signal, these flip-flops 20 are set so that the corresponding cathode ray tubes 21 are turned on or off. Furthermore, the display set and reset address generating circuit 15 also generates an address signal and a reset signal, and the reset signal is received by a reset address discriminating circuit 26 corresponding to the address. The reset signal is outputted from a line drive circuit 27 of the corresponding line to the reset terminals of the flip-flops 20, thereby resetting these flip-flops 20.
If the time interval between the generation of the set signal and the generation of the reset signal is constant, then the brightness of each cathode ray tube 21 corresponds to the data supplied from the data comparator 18. The brightness of the each cathode ray tube 21, i.e., the brightness of the entire screen of the display board can be controlled by changing the time interval between the generation of the two signals.
Graphic data read out from the graphic data memory 9 are supposed on video data through the OR circuit 33, and graphics are displayed on the screen. Since data read out from the blanking data memory 10 are inputted to the inhibit terminal of the AND circuit 32 through the AND circuit 29 and OR circuit 31, video data are blanked in accordance with the blanking data.
Today, in addition to standardized video signals according to NTSC, PAL, SECAM, etc., various video signals produced by computer systems are used. Such video signals including standardized video signals are different in form such as the number of scanning lines. Therefore, it is very difficult for one display apparatus in which display elements are fixedly arranged in a matrix form to reproduce all kinds of video signals.
When the frequency band of a video signal is F, a horizontal display period is T.sub.H, and a vertical display period is T.sub.V, the numbers m and n of vertical and horizontal display elements required for reproducing the video signal are T.sub.V /T.sub.H and F.multidot.T.sub.H, respectively (m=T.sub.V /T.sub.H and n=F.multidot.T.sub.H). If a display apparatus has a screen consisting of M number of display elements along the horizontal direction and N number of display elements along the vertical direction, the original video signal can principally be reproduced in a case that M&gt;m and N&gt;n. A prior art display apparatus is not provided with signal interpolation means for interpolating video signals along the horizontal and vertical directions. Therefore, the prior art display apparatus in which M&lt;m and N&lt;n has a problem in that the original video signal cannot be correctly reproduced.